Two mask floating gate EEPROM and method of making

ABSTRACT

There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a floating gate layer using a first photoresist mask to form a floating gate rail and doping an active area using the floating gate rail as a mask to form source and drain regions in the active area. The method also includes patterning a control gate layer, a control gate dielectric layer, the floating gate rail, a tunnel dielectric layer and the active area using a second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.

This application is a divisional of U.S. application Ser. No.10/066,376, filed Feb. 5, 2002, which is a continuation-in-part of U.S.application Ser. No. 09/927,648, filed on Aug. 13, 2001, which areincorporated by reference in their entirety. This application alsoclaims benefit of priority of provisional application Ser. No.60/279,855 filed on Mar. 28, 2001, which is incorporated by reference inits entirety.

FIELD OF THE INVENTION

The present invention is directed generally to semiconductor devices andmethods of fabrication and more particularly to a nonvolatile EEPROMmemory device and method of fabrication.

BACKGROUND OF THE INVENTION

U.S. Pat. No. 5,768,192, issued to B. Eitan, and the technical articleentitled “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile MemoryCell” by B. Eitan et al. in IEEE Electron Device Letters, vol. 21, No.11, November 2000, pp. 543-545 teach a nonvolatile semiconductor memorycell which uses asymmetrical charge trapping in the nitride chargestorage layer of the Oxide-Nitride-Oxide (ONO) stack to store two bitsin one cell. The cell is written by hot electron injection into thecharge storage layer above the drain junction. The cell is read in theopposite direction to which it was written, i.e., voltages are appliedto the source and gate, with the drain grounded. The memory cell isconstructed in a p-type silicon substrate. However, thissilicon-oxide-nitride-oxide-silicon (SONOS) 1TC memory requires LOCOS(localized oxidation of silicon) isolation regions, which cause the cellarea to be larger than desirable, and leads to a less than optimum celldensity and increases the number of photolithographic masking steps.

Another type of prior art memory device is disclosed in the technicalarticle entitled “A Novel Cell Structure for Giga-bit EPROMs and FlashMemories Using Polysilicon Thin Film Transistors” by S. Koyama in 1992Symposium on VLSI Technology Digest of Technical Papers, pp. 44-45. Asshown in FIG. 1, each memory cell is a “self-aligned” floating gate celland contains a polycrystalline silicon thin film transistor electricallyerasable programmable read only memory (TFT EEPROM) over an insulatinglayer. In this device, the bit lines extend in the direction parallel tothe source-channel-drain direction (i.e., the bit lines extend parallelto the charge carrier flow direction). The word lines extend in thedirection perpendicular to the source-channel-drain direction (i.e., theword lines extend perpendicular to the charge carrier flow direction).The TFT EEPROMs do not contain a separate control gate. Instead, theword line acts as a control gate in regions where it overlies thefloating gates.

The layout of Koyama requires two polycide contact pads to be formed tocontact the source and drain regions of each TFT. The bit lines areformed above the word lines and contact the contact pads through contactvias in an interlayer insulating layer which separates the bits linesfrom the word lines. Therefore, each cell in this layout is not fullyaligned, because the contact pads and the contact vias are eachpatterned using a non-self-aligned photolithography step. Therefore,each memory cell has an area that is larger than desirable, and leads toa less than optimum cell density. The memory cell of Koyama is alsocomplex to fabricate because it requires the formation of contact padsand bit line contact vias, which requires separate photolithographicmasking steps. Furthermore, the manufacturability of the device ofKoyama is less than optimum because both bit lines and word lines have anon-planar top surface due to the non-planar underlying topography. Thismay lead to open circuits in the bit and word lines.

BRIEF SUMMARY OF THE INVENTION

A preferred embodiment of the present invention provides a floating gatetransistor, comprising a channel island region, a source region locatedadjacent to a first side of the channel island region, a drain regionlocated adjacent to a second side of the channel island region, atunneling dielectric located above the channel island region and afloating gate having a first, second, third and fourth side surfaces,wherein the floating gate is located above the tunneling dielectric. Thetransistor also comprises a control gate dielectric located above thefloating gate and a control gate located above the control gatedielectric. The first and second side surfaces of the control gate arealigned to third and fourth side surfaces of the channel island region,and to third and the fourth side surfaces of the floating gate.

Another preferred embodiment of the present invention provides a methodof making a floating gate transistor, comprising providing asemiconductor active area, forming a tunnel dielectric layer over theactive area, forming a floating gate layer over the tunnel dielectriclayer, forming a first photoresist mask over the floating gate layer,patterning the floating gate layer using the first photoresist mask toform a floating gate rail and doping the active area using the floatinggate rail as a mask to form source and drain regions in the active area.The method further comprises forming an intergate insulating layeradjacent to lower portions of side surfaces of the floating gate rail,forming a control gate dielectric layer over and adjacent to upperportions of the side surfaces of the floating gate rail, forming acontrol gate layer over the control gate dielectric layer, forming asecond photoresist mask over the control gate layer, and patterning thecontrol gate layer, the control gate dielectric layer, the floating gaterail, the tunnel dielectric layer and the active area using the secondphotoresist mask to form a control gate, a control gate dielectric, afloating gate, a tunnel dielectric and a channel island region.

Another preferred embodiment of the present invention provides a methodof forming an array of floating gate transistors, comprising forming atleast portions of a plurality of floating gates over a tunnel dielectriclocated over a semiconductor active area, doping the active area usingthe at least portions of the plurality of floating gates as a mask toform a plurality of bit lines in the active area and forming anintergate insulating layer between lower portions of side surfaces ofthe at least portions of the plurality of floating gates. The methodfurther comprises forming a control gate dielectric on exposed uppersurfaces of the at least portions of the floating gates and on exposedupper portions of side surfaces of the at least portions of the floatinggates, and forming a plurality of word lines over the control dielectricand over the intergate insulating layer.

Another preferred embodiment of the present invention provides method ofmaking a floating gate transistor, comprising forming the entirefloating gate transistor using two photolithographic masking steps.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is diagram of the process flow of a method of making a prior artmemory device.

FIG. 2 is a side cross-sectional view of an in process memory arrayafter the formation of the floating gate rails according to the firstpreferred embodiment of the present invention.

FIG. 3 is a top view of FIG. 2.

FIG. 4 is a side cross-sectional view of an in process memory arrayafter floating gate rail patterning and bit line implantation andsilicidation according to the first preferred embodiment of the presentinvention. The cross-section is perpendicular to the bit lines.

FIG. 5 is a top view of FIG. 4.

FIG. 6 is a side cross-sectional view of an in process memory arrayafter the formation of the intergate insulating layer according to thefirst preferred embodiment of the present invention. The cross-sectionis perpendicular to the bit lines.

FIG. 7 is a side cross-sectional view of the array after the formationof the control gate layer according to the first preferred embodiment ofthe present invention. The cross-section is perpendicular to the bitlines.

FIG. 8 is a side cross-sectional view of the array after the patterningof the control gate layer according to the first preferred embodiment ofthe present invention. The cross-section is taken along line A-A′ inFIG. 7, and is parallel to the bit lines.

FIG. 9 is a top view of FIG. 8.

FIG. 10 is a three dimensional view of FIGS. 8 and 9.

FIG. 11 is a side cross-sectional view of the array according to thesecond preferred embodiment of the present invention. The cross-sectionis perpendicular to the bit lines.

FIGS. 12-13 are schematic side cross-sectional views of angled ionimplantation methods to form asymmetric source and drain regions of thesecond preferred embodiment of the present invention.

FIG. 14 is a schematic side cross-sectional view of a three dimensionalarray according to the third preferred embodiment of the presentinvention.

FIGS. 15-18 are schematic side cross-sectional views of formation ofinterconnects between device levels according to a fourth preferredembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present inventors have realized that memory cell area is enlarged bymisalignment tolerances that are put into place to guarantee completeoverlap between features on different layers. Thus, the presentinventors have developed a fully aligned memory cell structure whichdoes not require misalignment tolerances. Therefore, such a cellstructure has a smaller area per bit (i.e., per cell) and uses fewermask steps. The fully aligned cell structure increases memory densityand decreases die size and cost. Furthermore, by optionally stacking thecells vertically in the Z-direction, the memory density is furtherincreased, which leads to further decreases in the die size and cost.

As described with respect to the preferred embodiments of the presentinvention, an entire floating gate EEPROM transistor may be made usingonly two photolithographic masking steps. This decreases the processcost and complexity and ensures the precise alignment or self-alignmentof the layers of the transistor, since many of these layers arepatterned together using the same photoresist mask.

For example, by patterning the control and floating gates using the samemask as the channel results in a channel island which has at least twoside surfaces which are aligned to the floating and control gates.Furthermore, forming channel regions as islands and then filling thetrenches between the islands with an insulating layer creates trenchisolation between adjacent transistors without requiring an extraphotolithographic masking step. In contrast, an extra photolithographicmasking step is required to form prior art LOCOS or trench isolationbetween transistors.

Furthermore, the separate photolithographic masking step to form bitlines of the prior art process of FIG. 1 may be eliminated by formingthe bit lines using the same masking step used to form the floatinggates. For example, the floating gate layer is patterned only in onedirection to form floating gate rails or strips. Then, the semiconductoractive region portions exposed between the floating gate rails isimplanted and/or silicided to form conductive rails or strips extendingparallel to the floating gate rails. These conductive rails in theactive region act as the bit lines. These bit lines are then covered byan intergate insulating layer which is formed in self-alignment betweenthe floating gate rails. The floating gate rails are then patterned toform discrete floating gates using the same mask as is used to form thechannel regions and the control gate. Since the intergate insulatinglayer covers the bit lines during this etching step, the bit lines arenot etched during the channel etching step. The portions of the bitlines adjacent to the patterned floating gates act as the source anddrain of a given EEPROM transistor.

In this configuration, bit line contact pads (i.e., source and drainelectrodes) and bit line contact vias are not required because the bitlines may be formed in self-alignment with the EEPROM floating gates.Furthermore, since the EEPROMs are fully aligned or self-aligned, thebit and word lines may have a substantially planar upper surface, whichimproves the reliability of the device.

The method of making the array of EEPROM transistors 1 according to thefirst preferred embodiment of the present invention will now bedescribed in detail with references to FIGS. 2-10. It should be notedthat the present invention is not limited to an array of transistors,and includes the formation of a single transistor. It should also benoted that the array 1 does not have to be formed in a silicon layerlocated on an insulating surface (i.e., does not have to be formed as aTFT array), and may instead be formed in a bulk silicon substrate toform a bulk MOSFET EEPROM array.

A substrate having an insulating surface (i.e., a Silicon-On-Insulator(SOI) substrate) is provided for the formation of the memory array. Thesubstrate may comprise a semiconductor (i.e., silicon, GaAs, etc.) wafercovered with an insulating layer, such as a silicon oxide or nitridelayer, a glass substrate, a plastic substrate, or a ceramic substrate.In a preferred aspect of the first embodiment, the substrate is amonocrystalline bulk silicon substrate that has received priorprocessing steps, such as forming CMOS (complementary metal oxidesemiconductor) transistors in the substrate. The CMOS transistors maycomprise peripheral or driver circuitry for the memory array. In themost preferred aspect, the circuitry comprises row and column addressdecoders, column input/outputs (I/O's), and other logic circuitry.However, if desired, the driver circuitry may be formed on an insulatingsubstrate, such as a silicon-on-insulator substrate, a glass substrate,a plastic substrate, or a ceramic substrate. The silicon-on-insulatorsubstrate may be formed by any conventional method, such as waferbonding, Separation by Implantation of Oxygen (SIMOX), and formation ofan insulating layer on a silicon substrate. After the peripheralcircuitry is completed, an interlayer insulating layer (also known as aninterlayer dielectric) 3 is conformally deposited over the circuitry asshown in FIG. 2. The interlayer insulating layer 3 may comprise one ormore of any suitable insulating layers, such as silicon oxide, siliconnitride, silicon oxynitride, PSG, BPSG, BSG, spin-on glass and/or apolymer dielectric layer (such as polyimide, etc.). The interlayerinsulating layer 3 is preferably planarized using chemical-mechanicalpolishing (CMP), etch back and/or any other means.

A semiconductor active area layer 5 is then deposited over theinsulating layer 3 to complete the SOI substrate. The semiconductorlayer will be used for the transistor active areas. Layer 5 may have anydesired thickness, such as 10 to 120 nm, preferably less than 100 nm,most preferably less than 30 nm. Layer 5 is chosen so that in depletionregime the space charge region below the transistor gate extends overthe entire layer. The layer 5 may be thinned to the desired thicknessusing wet silicon etching or by sacrificial oxidation following by a wetoxide etch. Preferably, the semiconductor layer 5 comprises an amorphousor polycrystalline silicon layer doped with first conductivity typedopants. For example, layer 5 may be p-type doped by in-situ dopingduring deposition, or after deposition by ion implantation or diffusion.

If desired, the crystallinity of the semiconductor layer 5 may beimproved by heating the layer 5. In other words, an amorphous siliconlayer may be recrystallized to form polysilicon or a grain size of apolysilicon layer may be increased. The heating may comprise thermal orlaser annealing the layer 5. If desired, catalyst inducedcrystallization may be used to improve the crystallinity of layer 5. Inthis process, a catalyst element such as Ni, Ge, Mo, Co, Pt, Pd, asilicide thereof, or other transition metal elements, is placed incontact with the semiconductor layer 5. Then, the layer 5 is thermallyand/or laser annealed. During the annealing, the catalyst element eitherpropagates through the silicon layer leaving a trail of large grains, orserves as a seed where silicon crystallization begins. In the lattercase, the amorphous silicon layer then crystallizes laterally from thisseed by means of solid phase crystallization (SPC).

It should be noted that the deposition of amorphous or polysilicon layer5 may be omitted if a single crystal SOI substrate is used. In thiscase, using the SIMOX method, oxygen ions are implanted deep into asingle crystal silicon substrate, forming a buried silicon oxide layertherein. A single crystal silicon layer remains above the buried siliconoxide layer.

Next, the surface of the active area layer 5 is preferably cleaned fromimpurities and a native oxide is removed. A tunnel dielectric 7 isformed on the active area layer 5. Preferably, the tunnel dielectriccomprises a thermally grown silicon oxide layer (i.e., a silicon dioxidelayer grown on the silicon layer 5 by exposing layer 5 to an oxygencontaining atmosphere to convert a top portion of layer 5 to silicondioxide). The tunnel dielectric has a thickness of 5 nm to 10 nm,preferably 7 nm. It should be noted that different layer thicknesses anddifferent materials, such as silicon nitride or silicon oxynitride, maybe used instead.

After the tunnel dielectric 7 is formed, a floating gate layer 9 isdeposited over, and preferably directly on the tunnel dielectric 7. Thefloating gate layer 9 preferably comprises a polysilicon layer, such asan N+ polysilicon layer. Such a polysilicon layer may have anyappropriate thickness, such as 100 to 300 nm, preferably 200 nm, and anyappropriate dopant concentration, such as 10¹⁹-10²¹ cm⁻³, preferably10²⁰ cm⁻³.

If desired, an optional hardmask or etch stop layer 11, such as asilicon oxide layer or a dual lower silicon oxide/upper silicon nitridefilm, is formed on the surface of the floating gate layer 9. Layer 11may have any appropriate thickness, such as, for example 20-200 nm,preferably 50 nm. Materials other than silicon oxide and silicon nitridemay be used for layer 11, if desired.

Next, a bit line pattern is transferred to the in process array using areverse bit line mask, as shown in FIG. 2. For example, a positivephotoresist layer 13 is formed over the hardmask layer 11 and thenexposed through the reverse bit line mask and developed. Of course, if anegative photoresist is used, then the clear and the opaque areas of thebit line mask are reversed.

The photoresist mask 13 features are etched into the hardmask layer 11,and the floating gate layer 9, to form a plurality of rail stacks 15, asshown in FIG. 2. The tunnel dielectric 7 serves as an etch stop layer.Then, the photoresist mask 13 is stripped from the patterned gate railstacks 15.

FIG. 3 illustrates the top view of the in process array shown in FIG. 2.As shown in FIG. 3, the rail stacks 15 are in the shape of strips, andcontain the floating gate rails 9 and the hardmask rails 11. The tunneldielectric 7 is exposed in the areas between the rail stacks 15. Ifdesired, an optional thin layer of silicon nitride, oxynitiride or oxideis grown to seal the exposed sidewalls of the floating gate rails 9.

The array bit lines 17 are formed by self-aligned ion implantation intothe active layer 5, using the rail stacks 15 as a mask, as shown in FIG.4. The photoresist layer 13 is removed prior to the implantation.Alternatively, it may be left on the rail stacks 15 during thisimplantation. The ion implantation is carried out through the tunneldielectric 7. However, if desired, the portions of the tunnel dielectric7 between the floating gate rails 9 may be removed prior to the ionimplantation.

Channel regions 19 in the active layer 5 are located below the floatinggate rails 9. The bit lines 17 are doped with a second conductivity typedopant different from the first conductivity type dopant of the channels19. Thus, if the channels 19 are p-type doped, then the bit lines 17 aren-type doped, and vice-versa.

Next, optional sidewall spacers 21 are formed on the sidewalls of therail stacks 15, as shown in FIG. 4. Preferably, the spacers 21 comprisesilicon oxide or silicon nitride. Most preferably, the spacers comprisea different material from the hardmask layer. The spacers 21 arepreferably formed by conformal deposition of a silicon oxide layer overthe stacks 15, followed by an anisotropic oxide etch. The spacer etchprocess concludes with an etch process for the tunnel dielectric 7 toexpose the bit lines 17. Doping in the bit lines 17 may be increased atthis time by additional self-aligned ion implantation, using the railstacks 15 and spacers 21 as a mask, if desired. In this case, theimplantation before spacer formation is used to form lightly dopedportions or extensions of the source/drain (LDD) portions (about 1×10¹⁶to about 1×10¹⁸ cm⁻³ doping concentration) while the doping after spacerformation is used to form heavily doped source and drain regions (about1×10¹⁹ to about 1×10²¹ cm⁻³ doping concentration). Preferably, the bitlines a n-type doped. However, p-type doping may be used instead. Theformation of the spacers 21 and the lightly doped extensions may beomitted if desired.

The salicide process is then used to form silicide regions 23 in the topof the bit lines 17 in a self-aligned fashion, as shown in FIG. 4. Thesalicide process comprises three steps. First a layer of metal, such asTi, W, Mo, Ta, etc., or a transition metal such as Co, Ni, Pt or Pd isblanket deposited over the exposed bit line regions 17, the sidewallspacers 21 and the hardmask layer 11 of the rail stacks 15. The array isannealed to perform a silicidation by direct metallurgical reaction,where the metal layer reacts with the silicon in regions 17 to form thesilicide regions 23 over regions 17. The unreacted metal remaining onthe spacers 21 and the hardmask layer 11 is removed by a selective etch,e.g., by a piranha solution. The silicide regions 23 comprise portionsof the bit lines 17 in addition to the previously doped silicon regionsin the active layer 5.

FIG. 5 shows the top view of the device in FIG. 4 at this stage in theprocessing. The bit lines 17 containing silicide regions 23 extend asstrips parallel to the rail stacks 15.

A conformal intergate insulating layer 25 is then deposited to fill thetrenches above the bit lines 17 and between the floating gate rails 15and sidewall spacers, as shown in FIG. 6 (the sidewall spacers 21 aremerged into layer 25 in FIG. 6). The insulating layer 25 may compriseany insulating material, such as silicon oxide, silicon oxynitride,phosphosilicate glass (PSG), borophosphosilicate glass (BPSG),borosilicate glass (BSG), spin-on glass, a polymer dielectric layer(such as polyimide, etc.), and/or any other desired insulating material.Preferably, the intergate insulating layer is an isolation silicon oxidelayer deposited by a high density plasma (HDP) method.

The intergate insulating layer 25 is formed over and between the railstacks 15 (i.e., over and adjacent to the floating gate rails 9). Theintergate insulating layer 25 is then etched back such that theintergate insulating layer 25 remains adjacent to lower portions 27 ofthe floating gate rail side surfaces, below top portions 29 of thefloating gate rail side surfaces. Thus, the top portions 29 of the sidesurfaces of the floating gate rails 9 are exposed during this etchback.Furthermore, the top portions of the sidewall spacers 21 and thehardmask layer 11 are removed from the floating gate rails 9 during theetchback, as shown in FIG. 6.

A control gate dielectric layer 31 (also known as an inter-polydielectric) is formed over the floating gate rails 9, as shown in FIG.7. The control gate dielectric layer 31 is formed on the upper portions29 of the side surfaces of the floating gate rail 9 and on the topsurface of the floating gate rail 9. The control gate dielectric layer31 may have any appropriate thickness, such as 8 to 20 nm, preferably 12nm of silicon oxide equivalent. The control gate dielectric may compriseseveral dielectric materials with varying dielectric permittivities. Thesilicon oxide equivalent is silicon oxide of such thickness that whenused as a dielectric in a capacitor, it yields the same capacitance perunit area as the control gate dielectric. The control gate dielectriclayer 31 may be grown on the control gate by thermal oxidation ordeposited by CVD or other means. The control gate dielectric maycomprise silicon oxide, silicon nitride, silicon oxynitride, or a stackcomprising a thermally grown silicon oxide layer, a LPCVD depositedsilicon nitride layer and a high temperature LPCVD deposited siliconoxide (HTO) layer.

If desired, the top surface and the upper portions 29 of the sidesurfaces of the floating gate rails 9 may be roughened prior to formingthe control gate dielectric layer. The roughening may be accomplished byetching the exposed polysilicon of the rails 9 with an etching mediumwhich selectively attacks polysilicon grain boundaries, such as wetetching with NH₃OH.

The control gate layer 33 is then deposited over the entire device, asshown in FIG. 7. The control gate layer 33 is formed on the control gatedielectric layer 31 such that the control gate layer 33 is located overthe top surface of the floating gate rails 9 and laterally adjacent tothe upper portions 29 of the side surfaces of the floating gate rails.Since the control gate is located adjacent to the top and sides of thefloating gate, this increases the capacitance between the floating andcontrol gates. Preferably, the control gate layer 33 comprises amultilayer stack comprising a first N+ polysilicon layer, a silicidelayer (such as a TiSi or WSi, etc.) and a second N+ polysilicon layer.The polysilicon layers are preferably 100-300 nm thick, such as 200 nmthick. The silicide layer is preferably 50 to 100 nm thick, such as 60nm thick. The lower polysilicon layer fills in the openings between thefloating gates and overlies the control gate dielectric. Alternatively,the control gate layer can also be a single layer of silicide, metal, orany other combination of heavily doped amorphous or polycrystallinesilicon, silicide, and/or metal.

Next, a second photoresist mask 35 is formed by applying a photoresistlayer over the control gate layer 33, exposing it through the word linemask and developing it. The second photoresist mask 35 is used as a maskto anisotropically etch the control gate layer 33, the control gatedielectric layer 31, the floating gate rails 9, the tunnel dielectriclayer 7 and the active layer 5 to form a plurality of control gates 43,a plurality of control gate dielectrics 41, a plurality of floatinggates 49, a plurality of tunnel dielectrics 47 and a plurality ofchannel island regions 19, as shown in FIG. 8. Photoresist mask 35 isshown in dashed lines to indicate that it has already been removed inthe array of FIG. 8. FIG. 8 is a cross sectional view along line A-A′ inFIG. 7.

Each control gate 43, control gate dielectric 41, floating gate 49,tunnel dielectric 47 and channel island region 19 comprise a second railstack 45 as shown in FIG. 8. Thus, the sidewalls of the layers of therail stacks 45 are aligned since the rail stacks 45 were formed duringone etching step using the same mask 35.

If desired, the exposed sidewalls of the channel region islands 19, thefloating gates 49 and the control gates 43 sidewalls may be optionallysealed by growing a thin layer of silicon nitride or oxide on them, forexample by thermal nitridation or oxidation. This completes constructionof the memory array 1. An insulating fill layer 50 is then depositedbetween the second rail stacks 45, and if necessary planarized bychemical mechanical polishing or etchback, over the control gates 43.Layer 50 acts as trench isolation fill between the adjacent channelisland regions 19. Layer 50 preferably comprises the same material asthe interlayer insulating layer 3.

FIG. 9 is a top view and FIG. 10 is a three dimensional view of memoryarray 1 after the second photoresist mask 35 is removed and layer 50 isformed. The array of EEPROMs shown in FIGS. 8-10 contains a plurality ofbit line columns 17. Each bit line 17 contacts the source or the drainregions 57 of the TFT EEPROMs 51 (one exemplary memory cell or TFTEEPROM 51 is delineated by a dotted-dashed line in FIG. 9). The sourceand drain regions 57 are portions of the bit lines 17 that are locatedadjacent to the floating gates 49. Thus, the bit lines and the sourceand drain regions are formed in the same step without requiring an extraphotolithographic masking step. The columns of bit lines 17 extendsubstantially perpendicular to the source-channel-drain direction of theTFT EEPROMs 51 (i.e., at least a portion of the bit lines extends 0-20degrees from this perpendicular direction). The bit lines 17 compriserails which are located under the intergate insulating layer 25.

It should be noted that in a memory array 1, the designations “source”and “drain” are arbitrary. Thus, the regions 57 may be considered to be“sources” or “drains” depending on which bit line 17 a voltage isprovided. Furthermore, since no field oxide regions are preferably usedin this memory array, each region 57 is located between two floatinggates 49. Therefore, a particular region 57 may be considered to be a“source” with respect to one adjacent floating gate 49, and a “drain”with respect to the other adjacent floating gate 49. A source region 57is located adjacent to a first side of the channel island region 19,while a drain region 57 located adjacent to a second side of the channelisland region 19, such that the channel region is located between thesource and drain regions 57. Furthermore, the term “rail” and “railstack” are not limited to strips which extend in only one direction, andthe “rails” and “rail stacks” may have curves or bends and extend inmore than one direction.

The array 1 also contains a plurality of word lines 53 which contain thecontrol gates 43. In other words, the control gate 43 of each transistorcomprises a portion of a word line 53. The rows of word lines 53 extendsubstantially parallel to the source-channel-drain direction of the TFTEEPROMs 51 (i.e., at least a portion of the word lines extends 0-20degrees from this parallel direction).

The floating gates 49 comprise posts located between the channel islands19 and the control gates 43. The posts 49 have four side surfaces asshown in FIGS. 6, 7, 8 and 9. The first 55 and second 56 side surfacesof the control gate 43 are aligned to third 59 and fourth 61 sidesurfaces of the channel island region 19, and to third 63 and the fourth65 side surfaces of the floating gate 49, as shown in FIG. 8.Furthermore, the first 55 and the second 56 side surfaces of the controlgate 43 are aligned to side surfaces of the control gate dielectric 41and to side surfaces of the tunneling dielectric 47, as shown in FIG. 8.

The word line photolithography step does not require misalignmenttolerances, since the word lines 53 are patterned using the same mask asthe floating gate rails 9 and the active layer 5 (i.e., channel regions19) of each TFT 51 in the cell. Therefore, the word lines 53 are notonly aligned to the floating gates 49 of the TFT EEPROMs 51 but are alsoaligned to the channel regions 19 of each memory cell. Furthermore,during the same etching step, the adjacent control gates, floating gatesand channel islands are isolated from each other. By using a fullyaligned memory cell, the number of expensive and time consumingphotolithography steps are reduced. Furthermore, since no misalignmenttolerances for each cell are required, the cell density is increased.Another advantage of the device of the first embodiment is that since athick intergate insulating layer 25 is located between the bit lines 17and the word lines 53, the parasitic capacitance and a chance of a shortcircuit between the bit lines and the word lines are decreased.

The nonvolatile memory array 1 may be programmed and erased by variousconventional mechanisms. For example, the cells or TFT EEPROMs 51 of thearray may be programmed or written by applying a programming voltagebetween the source and drain regions to achieve channel hot carrier(e.g., electron) injection into the floating gate 49. The cells or TFTs51 of the array may be erased in blocks by applying an erase voltagebetween the control gate and a source or a drain to achieveFowler-Nordheim carrier (i.e., electron) tunneling from the floatinggate to the channel.

In a second preferred embodiment of the present invention, the array 100contains cells or TFTs 151 which have asymmetric source and drainregions 157, as shown in FIG. 11. The drain overlap with the floatinggate 149 is much larger than the source overlap with the floating gate149. In FIG. 11, a region 157 that acts as a source for one floatinggate 149 acts as a drain for an adjacent floating gate 149. The otherfeatures of the TFTs 151 are the same as those of TFTs 51 described inthe first preferred embodiment.

Due to the floating gate 149 to drain 157 overlap, the array 100 may beprogrammed or written bitwise by Fowler-Nordheim tunneling from thefloating gate 149 to the drain 157. The control gate 143 is grounded,while a programming voltage is applied to the asymmetric drain regions157, while the source regions 157 float. Since the source region isoffset from the floating gate, no tunneling occurs from the floatinggate to the source. This programming step decreases the thresholdvoltage of the TFT 151.

The cells or TFTs 151 of the array 100 may be erased in blocks byapplying a high erase voltage to the control gate and grounding thesource and drain regions to achieve Fowler-Nordheim carrier (i.e.,electron) tunneling from the channel to the floating gate. Thisprogramming increases the threshold voltage of the TFT 151.

The asymmetric source and drain regions 157 may be formed by any desiredmethod. For example, in one preferred method shown in FIG. 12, thesource and drain regions 157 are formed by performing an angled ionimplant 161 using the first rail stack 115 as a mask. In FIG. 12, theangled implant 161 comprises implanting heavily doped source and drainregions 157. If desired to form lightly doped portions of the sourceregions 163, then a lightly doped source region 163 is implanted at asmaller angle 165 sufficient to achieve an offset source as shown inFIG. 13.

The first and second preferred embodiments describe and illustrate across-point array of word lines and bit lines at a horizontal level anda method of making thereof. Each memory cell consists of a singleprogrammable field effect transistor (i.e., TFT), with its source anddrain connected to the j^(th) bit line and the (j+1)^(st) bit line,respectively, and a control gate being either connected to or comprisingthe k^(th) word line. This memory arrangement is known as the NORVirtual Ground (NVG) Array (also referred to as VGA). If desired, thememory array may also be arranged in non volatile flash memoryarchitectures other than VGA, such as NOR-type memory or Dual String NOR(DuSNOR) memory, for example. The DuSNOR architecture, where twoadjacent cell strings share a common source line but use different drainlines, is described in K. S. Kim, et al., IEDM-95, (1995) page 263,incorporated herein by reference. The DuSNOR memory may be fabricatedusing the same process as the VGA memory, except that an additionalmasking step is used to pattern the active area layer 5 to separate thedrain regions of adjacent cells. The active area 5 is patterned using athird mask to form a plurality of islands containing two EEPROMtransistors sharing a common source.

Alternatively, this additional masking step can instead be used toseparate both drains and sources of adjacent cells, thus achieving fullisolation of adjacent cell strings. The active area 5 is patterned usinga third mask to form a plurality of islands containing one EEPROMtransistor to form an array with separated drain and source lines. Thus,each cell does not share a source or a drain (i.e., bit) line with alaterally adjacent cell. This NOR-type memory array architecture isknown as Separated Source Line NOR (SSL-NOR) memory. The SSL-NOR arrayarchitecture is described in I. Fujiwara, et al., Proceedings ofNon-Volatile Semiconductor Memory Workshop (2000), page 117,incorporated herein by reference.

The process sequence of the first and second preferred embodiments ofthe present invention requires only two photolithographic masking stepsto form each cell. One masking step is for gate patterning/self alignedbit line formation. The other masking step is for word line patterning.The methods of the preferred embodiments of the present inventionexploit self-alignment to reduce alignment tolerances between the masks.The memory cell area achieved with the foregoing process is about 4 f²,where f is the minimum feature size (i.e. 0.18 microns in a 0.18 micronsemiconductor process). The term “about” allows for small deviations(10% or less) due to non-uniform process conditions and other smalldeviations from desired process parameters.

The array of the first and second preferred embodiments is very suitablefor vertical stacking of horizontal planar arrays to form a threedimensional array of device levels, each device level containing anarray TFT EEPROMs described above. FIG. 14 illustrates a threedimensional memory array 200 of the third preferred embodimentcontaining a plurality of device levels 202, the device levelscontaining the array 1 or 100 of TFT EEPROMs described above.

Each device level 202 of the array 200 is separated and decoupled in thevertical direction by an interlayer insulating layer 203. The interlayerinsulating layer 203 also isolates adjacent word lines 53 and adjacentportions of the active areas 5 below the respective word lines in eachdevice level 202. Connection between the bit lines, word lines andperipheral or driver circuits in the substrate 206 is made throughvertical interlevel interconnects 208.

FIGS. 15 through 18 illustrate a method of forming vertical interlevelinterconnects 208 between an upper device level 202 and a lower devicelevel 202 or driver circuits in the substrate 206, according to a fourthpreferred embodiment of the present invention. A photoresist mask 209 isformed by applying a photoresist layer over the first N+ polysiliconlayer of the control gate layer 33, exposing the photoresist layerthrough an interlevel interconnect mask and developing the photoresist,as shown in FIG. 15. The photoresist mask 209 is used to anisotropicallyetch the first N+ polysilicon layer 33, the control gate dielectriclayer 31, the floating gate rails 9, the tunnel dielectric layer 7, andthe active layer 5, stopping the etch on the interlayer insulating layer203 and the intergate insulating layer 25. Then, the insulating layers203 and 25 are etched anisotropically using mask 209 to form at leastone via extending to the lower device level 202 or substrate 206, asshown in FIG. 16. The use of the intergate insulating layer 25 as anetch stop allows the formation of a stepped via, as shown on the leftside of FIG. 16. The photoresist mask 209 is subsequently removed. Next,a conducting layer 211, comprising a metal layer, such as Ti, W, etc.,or a silicide layer, such as TiSi, WSi, etc., is deposited conformallyon the first heavily doped N+ polysilicon layer 33, followed byconformal deposition of an optional second N+ polysilicon layer 213. Ofcourse P+ polysilicon may be used instead of N+ polysilicon for theselayers. Next, the wordline photoresist mask 35 is formed over layer 213,as shown in FIG. 17. Then, as shown in FIG. 18, the control gate etchprocess is performed similar to that shown in FIG. 8, to form theplurality of the control gates 43, the plurality of the floating gates49, and the plurality of the channel island regions 19, as describedabove with respect to the first embodiment. The vertical interlevelinterconnects 208 are formed, as shown in FIG. 18. The patternedconducting layer 211 and the second polysilicon layer 213 form theinterconnects 208 as well as the upper portion of the control gates 43(i.e., an upper portion of the word lines or gate lines 53). Thus, atleast a portion of the word or gate line comprises the same layer(s) asthe interlevel interconnects.

Preferably, the array of nonvolatile memory devices 200 comprises amonolithic three dimensional array of memory devices. The term“monolithic” means that layers of each level of the array 200 weredirectly deposited on the layers of each underlying level of the array.A first array or device level 202 of TFT EEPROMs is provided over thesubstrate 206. The interlayer insulating layer 203 is formed over thisarray. Then, at least one or more additional arrays or device levels 202of TFT EEPROMs are monolithically formed on the interlayer insulatinglayer 203.

Alternatively, two dimensional arrays may be formed separately and thenpackaged together to form a non-monolithic three dimensional memoryarray 200. A plurality of arrays 1 or 100 of TFT EEPROMs are formed ondifferent silicon-on-insulator substrates. The substrates are thinned bypolishing or etching the back sides of the substrates. The arrays arethen attached or glued to each other to form a three dimensional memoryarray 200.

Preferably, the TFTs in a plurality of the levels 202 of the threedimensional array 200 of FIG. 14 undergo a recrystallization and/or adopant activation step at the same time. This reduces the devicefabrication time and cost. Furthermore, if each level of the array issubjected to a separate crystallization and/or dopant activationannealing, then the lower levels would undergo more annealing steps thanthe upper levels. This may lead to device non uniformity because thegrain size may be larger in the active areas of the lower levels and/orthe source and drain regions may have a different dopant distribution inthe lower levels than in the upper levels.

Each cell in one level 202 of the memory array 200 can be formed usingonly two photolithographic masking steps. However, additional maskingsteps may be needed to form contacts to the bit lines and the wordlines. The preferred aspects of the present invention may also beapplied to nonvolatile flash memory architectures other than VGA, DuSNORand SSL-NOR memory. Furthermore, the present invention is not limited toTFT EEPROM flash memory arrays, and also encompasses other semiconductordevices within its scope. For example, the self-aligned transistors maybe MOSFETs in a bulk substrate. These self-aligned transistors may beused as non-flash EEPROMs (i.e., EEPROMs where each transistor is erasedseparately), UV erasable PROMs (EPROMs), mask ROMs, dynamic randomaccess memories (DRAMs), liquid crystal displays (LCDs), fieldprogrammable gate arrays (FPGA) and microprocessors.

The foregoing description of the invention has been presented forpurposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise form disclosed, andmodifications and variations are possible in light of the aboveteachings or may be acquired from practice of the invention. Thedrawings and description were chosen in order to explain the principlesof the invention and its practical application. The drawings are notnecessarily to scale and illustrate the memory array in schematic blockformat. It is intended that the scope of the invention be defined by theclaims appended hereto, and their equivalents.

1. A method of making a floating gate transistor, comprising: providinga semiconductor active area; forming a tunnel dielectric layer over theactive area; forming a floating gate layer over the tunnel dielectriclayer; forming a first photoresist mask over the floating gate layer;patterning the floating gate layer using the first photoresist mask toform a floating gate rail; doping the active area using the floatinggate rail as a mask to form source and drain regions in the active area;forming an intergate insulating layer adjacent to lower portions of sidesurfaces of the floating gate rail; forming a control gate dielectriclayer over and adjacent to upper portions of the side surfaces of thefloating gate rail; forming a control gate layer over the control gatedielectric layer; forming a second photoresist mask over the controlgate layer; and patterning the control gate layer, the control gatedielectric layer, the floating gate rail, the tunnel dielectric layerand the active area using the second photoresist mask to form a controlgate, a control gate dielectric, a floating gate, a tunnel dielectricand a channel island region.
 2. The method of claim 1, comprisingforming the entire floating gate transistor using two photolithographicmasking steps.
 3. The method of claim 1, wherein forming an intergateinsulating layer adjacent to the side surfaces of the floating gate railcomprises: forming the intergate insulating layer over and adjacent tothe floating gate rail; and etching back the intergate insulating layersuch that the intergate insulating layer remains adjacent to the lowerportions of the floating gate rail side surfaces below the upperportions of the floating gate rail side surfaces.
 4. The method of claim3, further comprising: forming a hardmask over the floating gate layer;forming the first photoresist mask on the hardmask layer; and patterningthe hardmask layer and the floating gate layer using the firstphotoresist mask to form a first rail stack comprising a hardmask railand the floating gate rail.
 5. The method of claim 4, furthercomprising: implanting lightly doped portions of the source and drainregions using the first rail stack as a mask; forming sidewall spacerson the first rail stack; implanting heavily doped portions of the sourceand drain regions using the first rail stack and the sidewall spacers asa mask; forming a metal layer over the source and drain regions and overthe first rail stack; annealing the first metal layer to react the metallayer with the source and drain regions to selectively form metalsilicide regions on the source and drain regions; and selectivelyetching the unreacted metal layer remaining on the sidewall spacers andthe first rail stack.
 6. The method of claim 5, further comprising:selectively removing the hardmask and sidewall spacers from upperportions of the floating gate rail; forming the control gate dielectriclayer on the upper portions of the side surfaces of the floating gaterail and on the top surface of the floating gate rail; and forming thecontrol gate layer on the control gate dielectric layer such that thecontrol gate layer is located over the top surface of the floating gaterail and laterally adjacent to the upper portions of the side surfacesof the floating gate rail.
 7. The method of claim 4, further comprisingroughening the top surface and the upper portions of the side surfacesof the floating gate rail prior to forming the control gate dielectriclayer.
 8. The method of claim 4, wherein forming the source and drainregions comprises performing an angled implant using the first railstack as a mask to form source and drain regions which are asymmetricwith respect to the first rail stack.
 9. The method of claim 8, whereinthe angled implant comprises implanting heavily doped source and drainregions.
 10. The method of claim 9, further comprising implanting alightly doped portion of the source region perpendicular to the activearea.
 11. The method of claim 1, further comprising: patterning thefloating gate layer using the first photoresist mask to form a pluralityof floating gate rails; doping the active area using the floating gaterails as a mask to form a plurality of source and drain regions in theactive area; forming the intergate insulating layer between lowerportions of the side surfaces of the floating gate rails; forming thecontrol gate dielectric layer and the control gate layer over andadjacent to upper portions of the side surfaces of the floating gaterails; forming the second photoresist mask over the control gate layer;and patterning the control gate layer, the control gate dielectriclayer, the floating gate rails, the tunnel dielectric layer and theactive area using the second photoresist mask to form a plurality ofcontrol gates, a plurality of control gate dielectrics, a plurality offloating gates, a plurality of tunnel dielectrics and a plurality ofchannel island regions.
 12. The method of claim 11, wherein theintergate insulating layer protects the plurality of source and drainregions in the active area during the patterning of the floating gaterails and the active area.
 13. The method of claim 11, furthercomprising forming an insulating fill layer between adjacent second railstacks, wherein each second rail stack comprises one of the plurality ofcontrol gates, one the plurality of control gate dielectrics, one of theplurality of floating gates, one of the plurality of tunnel dielectricsand one of the plurality of channel island regions.
 14. The method ofclaim 11, wherein forming an intergate insulating layer adjacent to theside surfaces of the floating gate rail comprises: forming the intergateinsulating layer over and adjacent to the floating gate rails; andetching back the intergate insulating layer such that the intergateinsulating layer remains between the floating gate rails, adjacent tothe lower portions of the floating gate rail side surfaces below theupper portions of the floating gate rail side surfaces.
 15. The methodof claim 14, further comprising patterning the hardmask layer and thefloating gate layer using the first photoresist mask to form a pluralityof first rail stacks each comprising a hardmask rail and the floatinggate rail.
 16. The method of claim 15, further comprising: implanting aplurality of lightly doped portions of the source and drain regionsusing the first rail stacks as a mask; forming sidewall spacers on thefirst rail stacks; implanting a plurality of heavily doped portions ofthe source and drain regions using the first rail stacks and thesidewall spacers as a mask; forming a metal layer over the plurality ofsource and drain regions and over the first rail stacks; annealing thefirst metal layer to react the metal layer with the plurality of sourceand drain regions to selectively form metal silicide regions on theplurality of source and drain regions; and selectively etching theunreacted metal layer remaining on the sidewall spacers and the firstrail stacks.
 17. The method of claim 16, further comprising: selectivelyremoving the hardmask and sidewall spacers from upper portions of thefloating gate rails; forming the control gate dielectric layer on theupper portions of the side surfaces of the floating gate rails and onthe top surface of the floating gate rails; and forming the control gatelayer on the control gate dielectric layer such that the control gatelayer is located over the top surface of the floating gate rails andlaterally adjacent to the upper portions of the side surfaces of thefloating gate rails.
 18. The method of claim 17, further comprisingpatterning the active area using a third mask to form a plurality ofislands containing two EEPROM transistors sharing a common source toform a DuSNOR array.
 19. The method of claim 17, further comprisingpatterning the active area using a third mask to form a plurality ofislands containing one EEPROM transistor to form a SSL-NOR array withseparated drain and source lines.
 20. The method of claim 17, wherein:the step of doping the active area further comprises forming a pluralityof bit lines containing the plurality of source and drain regions,wherein the bit lines extend substantially perpendicular to asource-channel-drain direction; the step of forming metal silicideregions comprises forming a metal silicide on the plurality of bitlines; and the step of patterning the active area comprises etching theactive area to form a plurality of channel island regions withoutetching the bit lines containing the source and drain regions which arecovered by the intergate insulating layer.
 21. The method of claim 1,wherein providing the semiconductor active area comprises forming apolysilicon active layer over an interlayer insulating layer.
 22. Themethod of claim 21, wherein: forming the tunnel dielectric layer overthe active area comprises growing a thermal silicon oxide layer on thepolysilicon active layer; forming the floating gate layer over thetunnel dielectric layer comprises forming a polysilicon layer on thetunnel dielectric layer; forming the first photoresist mask over thefloating gate layer comprises forming the photoresist on a hardmasklayer located on the floating gate layer; patterning the floating gatelayer using the first photoresist mask to form a floating gate railcomprises anisotropically etching the hardmask layer and the floatinggate layer during one etching step using the first photoresist mask;doping the active area using the floating gate rail as a mask to formsource and drain regions in the active area comprises ion implanting thesource and drain regions using the floating gate rail as a mask; formingthe intergate insulating layer adjacent to the side surfaces of thefloating gate rail comprises forming the intergate insulating layer overand adjacent to the floating gate rail and etching back the intergateinsulating layer such that the intergate insulating layer remainsadjacent to the lower portions of the floating gate rail side surfacesbelow the upper portions of the floating gate rail side surfaces;forming the control gate dielectric layer comprises growing a thermalsilicon oxide layer on the floating gate rail, depositing a siliconnitride layer on the thermal silicon oxide layer and depositing asilicon oxide layer on the silicon nitride layer; forming the controlgate layer over the control gate dielectric layer comprises depositing apolysilicon layer and a silicide layer on the control gate dielectriclayer; forming the second photoresist mask over the control gate layercomprises forming the second photoresist mask on the control gate layer;and patterning the control gate layer, the control gate dielectriclayer, the floating gate rail, the tunnel dielectric layer and theactive area using the second photoresist mask comprises anisotropicallyetching the control gate layer, the control gate dielectric layer, thefloating gate rail, the tunnel dielectric layer and the active layer inone etching step to form second rail stacks.
 23. The method of claim 11,further comprising: forming an interlayer insulating layer below theactive area; forming at least one via extending through the interlayerinsulating layer to a lower device level or to a driver circuit in asubstrate; depositing at least a portion of the control gate layer inthe at least one via; and patterning the control gate layer to form theplurality of control gates and an interlevel interconnect which connectsthe floating gate transistor with a device on a lower device level orwith a driver circuit in the substrate.
 24. The method of claim 23,further comprising: forming a heavily doped polysilicon layer comprisinga lower portion of the control gate layer; forming the at least one viaextending through the heavily doped polysilicon layer; forming aconductive layer comprising an upper portion of the control gate layeron the heavily doped polysilicon layer and in the at least one via; andpatterning the heavily doped polysilicon layer and the conductive layerto form the plurality of control gates and the interlevel interconnect.25. A method of forming a monolithic three dimensional memory array,comprising: providing a first array of transistors of claim 11; formingan interlayer insulating layer over the array; and monolithicallyforming at least a second array of TFT EEPROMs on the interlayerinsulating layer.
 26. A method of forming a three dimensional memoryarray, comprising: providing a plurality of arrays of transistors ofclaim 11 on different silicon on insulator substrates; thinning thesubstrates; and attaching the arrays to each other to form a threedimensional memory array.
 27. A method of claim 8, further comprising:programming the floating gate EEPROM transistor by Fowler-Nordheimelectron tunneling from the floating gate to the drain region; anderasing the floating gate EEPROM transistor by Fowler-Nordheim electrontunneling from the channel island region to the floating gate.
 28. Amethod of forming an array of floating gate transistors, comprising:forming at least portions of a plurality of floating gates over a tunneldielectric located over a semiconductor active area; wherein the step offorming the at least portions of the plurality of floating gatescomprises: providing the semiconductor active area; forming a tunneldielectric layer over the active area; forming a floating gate layerover the tunnel dielectric layer; forming a first photoresist mask overthe floating gate layer and patterning the floating gate layer using thefirst photoresist mask to form the plurality of the floating gateportions comprising floating gate rails; doping the active area usingthe at least portions of the plurality of floating gates as a mask toform a plurality of bit lines in the active area; wherein the step ofdoping the active area comprises: doping the active area using thefloating gate rails as a mask to form the plurality of bit linescontaining transistor source and drain regions; forming an intergateinsulating layer between lower portions of side surfaces of the at leastportions of the plurality of floating gates; forming a control gatedielectric on exposed upper surfaces of the at least portions of thefloating gates and on exposed upper portions of side surfaces of the atleast portions of the floating gates; and forming a plurality of wordlines over the control dielectric and over the integrate insulatinglayer; wherein the steps of forming the control gate dielectric andforming the plurality of word lines comprise: forming a control gatedielectric layer and a control gate layer over and adjacent to upperportions of the side surfaces of the floating gate rails; forming asecond photoresist mask over the control gate layer; and patterning thecontrol gate layer, the control gate dielectric layer, the floating gaterails, the tunnel dielectric layer and the active area using the secondphotoresist mask to form the plurality of word lines containingtransistor control gates, a plurality of control gate dielectrics, aplurality of floating gates, a plurality of tunnel dielectrics and aplurality of channel island regions.
 29. The method of claim 28 whereinforming the intergate insulating layer comprises: forming the intergateinsulating layer over and adjacent to the floating gate rails; andetching back the intergate insulating layer such that the intergateinsulating layer remains between the floating gate rails, adjacent tothe lower portions of the floating gate rail side surfaces below theupper portions of the floating gate rail side surfaces.
 30. The methodof claim 29, further comprising: forming a hardmask layer over thefloating gate layer; and patterning the hardmask layer and the floatinggate layer using the first photoresist mask to form a plurality of firstrail stacks each comprising a hardmask rail and the floating gate rail.31. The method of claim 30, further comprising forming an insulatingfill layer between adjacent second rail stacks, wherein each second railstack comprises one of the plurality of word lines, one the plurality ofcontrol gate dielectrics, one of the plurality of floating gates, one ofthe plurality of tunnel dielectrics and one of the plurality of channelisland regions.
 32. The method of claim 31, further comprising:implanting a plurality of lightly doped portions of the source and drainregions using the first rail stacks as a mask; forming sidewall spacerson the first rail stacks; implanting a plurality of heavily dopedportions of the source and drain regions using the first rail stacks andthe sidewall spacers as a mask; forming a metal layer over the pluralityof bit lines, over the plurality of source and drain regions and overthe first rail stacks; annealing the first metal layer to react themetal layer with the plurality of bit lines and the plurality of sourceand drain regions to selectively form metal silicide regions on theplurality of bit lines and the plurality of source and drain regions;and selectively etching the unreacted metal layer remaining on thesidewall spacers and the first rail stacks.
 33. The method of claim 32,wherein: providing the semiconductor active area comprises forming apolysilicon active layer over an interlayer insulating layer; formingthe tunnel dielectric layer over the active area comprises growing athermal silicon oxide layer on the polysilicon active layer; forming thefloating gate layer over the tunnel dielectric layer comprises forming apolysilicon layer on the tunnel dielectric layer; forming the firstphotoresist mask over the floating gate layer comprises forming thephotoresist on the hardmask layer; patterning the floating gate layerusing the first photoresist mask to form a floating gate rail comprisesanisotropically etching the hardmask layer and the floating gate layerduring one etching step using the first photoresist mask; forming thecontrol gate dielectric layer comprises growing a thermal silicon oxidelayer on the floating gate rail, depositing a silicon nitride layer onthe thermal silicon oxide layer and depositing a silicon oxide layer onthe silicon nitride layer; forming the control gate layer over thecontrol gate dielectric layer comprises depositing a polysilicon layerand a silicide layer on the control gate dielectric layer; forming thesecond photoresist mask over the control gate layer comprises formingthe second photoresist mask on the control gate layer; and patterningthe control gate layer, the control gate dielectric layer, the floatinggate rail, the tunnel dielectric layer and the active area using thesecond photoresist mask comprises anisotropically etching the controlgate layer, the control gate dielectric layer, the floating gate rail,the tunnel dielectric layer and the active layer in one etching step toform the second rail stacks.
 34. A method of forming a monolithic threedimensional memory array, comprising: providing a first array offloating gate EEPROM transistors of claim 28; forming an interlayerinsulating layer over the array; and monolithically forming at least asecond array of TFT EEPROMs on the interlayer insulating layer.
 35. Amethod of forming a three dimensional memory array, comprising:providing a plurality of arrays of floating gate EEPROM transistors ofclaim 28 on different silicon on insulator substrates; thinning thesubstrates; and attaching the arrays to each other to form a threedimensional memory array.
 36. The method of claim 28 further comprising:forming an interlayer insulating layer below the active area; forming atleast one via extending through the interlayer insulating layer to alower device level or to a driver circuit in a substrate; depositing atleast a portion of a word line layer in the at least one via; andpatterning the word line layer to form the plurality of word lines andan interlevel interconnect which connects the array of transistors witha device on a lower device level or with a driver circuit in thesubstrate.
 37. The method of claim 36 further comprising: forming aheavily doped polysilicon layer comprising a lower portion of the wordline layer; forming the at least one via extending through the heavilydoped polysilicon layer; forming a conductive layer comprising an upperportion of the word line layer on the heavily doped polysilicon layerand in the at least one via; and patterning the heavily dopedpolysilicon layer and the conductive layer to form the plurality of wordlines and the interlevel interconnect.
 38. A method of making a floatinggate transistor, comprising forming the entire floating gate transistorusing two photolithographic masking steps wherein a channel islandregion and at least one of a control gate and a floating gate are etchedusing a same mask such that a semiconductor channel region of thefloating gate transistor is formed in the etched channel island region,the method comprising: providing a semiconductor active area; forming atunnel dielectric layer over the active area; forming a floating gatelayer over the tunnel dielectric layer; forming a first photoresist maskover the floating gate layer in a first photolithographic masking step;patterning the floating gate layer using the first photoresist mask toform a floating gate rail; doping the active area using the floatinggate rail as a mask to form source and drain regions in the active area;forming an intergate insulating layer adjacent to lower portions of sidesurfaces of the floating gate rail; forming a control gate dielectriclayer over and adjacent to upper portions of the side surfaces of thefloating gate rail; forming a control gate layer over the control gatedielectric layer; forming a second photoresist mask over the controlgate layer in a second photolithographic masking step; and patterningthe control gate layer, the control gate dielectric layer, the floatinggate rail, the tunnel dielectric layer and the active area using thesecond photoresist mask to form the control gate, a control gatedielectric, the floating gate, a tunnel dielectric and the channelisland region.
 39. The method of claim 38, wherein forming an intergateinsulating layer adjacent to the side surfaces of the floating gate railcomprises: forming the intergate insulating layer over and adjacent tothe floating gate rail; and etching back the intergate insulating layersuch that the intergate insulating layer remains adjacent to the lowerportions of the floating gate rail side surfaces below the upperportions of the floating gate rail side surfaces.
 40. The method ofclaim 39, further comprising: forming a hardmask over the floating gatelayer; forming the first photoresist mask on the hardmask layer;patterning the hardmask layer and the floating gate layer using thefirst photoresist mask to form a first rail stack comprising a hardmaskrail and the floating gate rail; implanting lightly doped portions ofthe source and drain regions using the first rail stack as a mask;forming sidewall spacers on the first rail stack; implanting heavilydoped portions of the source and drain regions using the first railstack and the sidewall spacers as a mask; forming a metal layer over thesource and drain regions and over the first rail stack; annealing thefirst metal layer to react the metal layer with the source and drainregions to selectively form metal silicide regions on the source anddrain regions; and selectively etching the unreacted metal layerremaining on the sidewall spacers and the first rail stack.
 41. Themethod of claim 40 further comprising: selectively removing the hardmaskand sidewall spacers from upper portions of the floating gate rail;forming the control gate dielectric layer on the upper portions of theside surfaces of the floating gate rail and on the top surface of thefloating gate rail; and forming the control gate layer on the controlgate dielectric layer such that the control gate layer is located overthe top surface of the floating gate rail and laterally adjacent to theupper portions of the side surfaces of the floating gate rail.
 42. Themethod of claim 28, wherein the step of forming the intergate insulatinglayer occurs after the step of doping the active area.